Product Descriptions

RK3368 is a low power, high performance processor for mobile phones, personal mobile internet device and other digital multimedia applications, and integrates octa-core CortexA53 with separately NEON coprocessor. 

Many embedded powerful hardware engines provide optimized performance for high-end application. RK3368 supports almost full-format H.264 decoder by 4Kx2K@30fps, H.265 decoder by 4Kx2K@60fps, also support H.264/MVC/VP8 encoder by 1080p@30fps, highquality JPEG encoder/decoder, and special image preprocessor and postprocessor.

Embedded 3D GPU makes RK3368 completely compatible with OpenGL ES3.1, OpenCL1.2 and DirectX 9.3. Special 2D hardware engine with MMU will maximize display performance and provide very smoothly operation.

RK3368 has high-performance external memory interface (DDR3/DDR3L /LPDDR2/LPDDR3) capable of sustaining demanding memory bandwidths, also provides a complete set of peripheral interface to support very flexible applications.

Product Features

The features listed below which may or may not be present in actual product, may be  subject to the third party licensing requirements. Please contact Rockchip for actual product  feature configurations and licensing requirements.

1.2.1 Micro Processor

•  Octa-core ARM Cortex-A53 MPCore processor, a high-performance, low-power and cached application processor

•  Two CPU clusters, with four CPU core for each cluster, One cluster is optimized for highperformance(big cluster) and the other is optimized for low power(little cluster)

•  Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation

•  ARMv8 Cryptography Extensions

•  In-order pipeline with symmetric dual-issue of most instructions.

•  Harvard Level 1 (L1) memory system with a Memory Management Unit (MMU).

•  Level 2 (L2) memory system providing cluster memory coherency, including an L2 cache.

•  Include VFP v3 hardware to support single and double-precision add, subtract, divide, multiply and accumulate, and square root operations

•  SCU ensures memory coherency between the four CPUs for each cluster

•  CCI400 ensures the memory coherency between the two clusters

•  Integrated 32KB L1 instruction cache , 32KB L1 data cache with 4-way set associative

•  512KB unified L2 Cache for big cluster, 256KB unified L2 Cache for little cluster

•  Trustzone technology support

•  Full coresight debug solution

•  Debug and trace visibility of whole systems

•  ETM trace support

•  Invasive and non-invasive debug

•  Ten separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenario

•  PD_A53_L0: 1st Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster

•  PD_A53_L1: 2nd Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster

•  PD_A53_L2: 3rd Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster

•  PD_A53_L3: 4th Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster

•  PD_SCU_L: SCU + L2 Cache controller, and including PD_A53_L0, PD_A53_L1, PD_A53_L2, PD_A53_L3, debug logic of little cluster

•  PD_A53_B0: 1st Cortex-A53 + Neon + FPU + L1 I/D Cache of big cluster

•  PD_A53_B1: 2nd Cortex-A53 + Neon + FPU + L1 I/D Cache of big cluster

•  PD_A53_B2: 3rd Cortex-A53 + Neon + FPU + L1 I/D Cache of big cluster

•  PD_A53_B3: 4th Cortex-A53 + Neon + FPU + L1 I/D Cache of big cluster

•  PD_SCU_B: SCU + L2 Cache controller, and including PD_A53_B0, PD_A53_B1, PD_A53_B2, PD_A53_B3, debug logic of big cluster

•  One isolated voltage domain to support DVFS

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