Product Features

• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)

• Bidirectional data strobe (DQS) transmitted/ received with data, that is, source-synchronous data capture (x16 has two – one per byte)

• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; centeraligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data (x16 has two – one per byte)

• Programmable burst lengths (BL): 2, 4, or 8

• Auto refresh 

– 64ms, 8192-cycle(Commercial & Industrial)

– 16ms, 8192-cycle (Automotive)

• Self refresh (not available on AT devices)

• Longer-lead TSOP for improved reliability (OCPL)

• 2.5V I/O (SSTL_2-compatible)

• Concurrent auto precharge option supported

• tRAS lockout supported (tRAP = tRCD)

Specifications

Actual product photos

Product Data Book：

For more product information, please download the PDF

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

We also provide ：