Product Details

Overview

This chapter provides an overview of the microprocessor features, including the major functional components.

Key Features

A block diagram of the MCF528x and MCF521x is shown in Figure 1-1. The main features are as follows:
• Static Version 2 ColdFire variable-length RISC processor
— Static operation
— On-chip 32-bit address and data path
— Processor core and bus frequency up to 80 MHz
— Sixteen general-purpose 32-bit data and address registers
— ColdFire ISA_A with extensions to support the user stack pointer register, and four new instructions for improved bit processing
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with one user-visible hardware breakpoint register (PC and address with optional data) that can be configured into a 1- or 2-level trigger
• On-chip memories
— 2-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters
(e.g., DMA, FEC) with standby power supply support
— 512 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
(256 Kbytes on the MCF5281 and MCF5214, no Flash on MCF5280)
– This product incorporates SuperFlash® technology licensed from SST.
• Power management
— Fully-static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
• Fast Ethernet Controller (FEC) (not available on the MCF5214 and MCF5216)
— 10BaseT capability, half- or full-duplex
— 100BaseT capability, half- or limited-throughput full-duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
— Media-independent interface (MII) to transceiver (PHY)
• FlexCAN 2.0B Module
— Includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard data and remote frames (up to 109 bits long)
– Extended data and remote frames (up to 127 bits long)
– 0–8 bytes data length
– Programmable bit rate up to 1 Mbit/sec
— Up to 16 message buffers (MBs)
– Configurable as receive (Rx) or transmit (Tx)
– Support standard and extended messages
— Unused message buffer (MB) space can be used as general-purpose RAM space
— Listen-only mode capability
— Content-related addressing
— No read/write semaphores
— Three programmable mask registers
– Global (for MBs 0-13)
– Special for MB14
– Special for MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— “Time stamp” based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Programmable I/O modes
— Maskable interrupts
• Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic
— Maskable interrupts
— DMA support
— Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two UARTs
— Transmit and receive FIFO buffers
• I2C module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable master bit rates
— Up to 16 pre-programmed transfers
• Queued analog-to-digital converter (QADC)
— 8 direct, or up to 18 multiplexed, analog input channels
— 10-bit resolution +/- 2 counts accuracy
— Minimum 7 μS conversion time
— Internal sample and hold
— Programmable input sample time for various source impedances
— Two conversion command queues with a total of 64 entries
— Sub-queues possible using pause mechanism
— Queue complete and pause software interrupts available on both queues
— Queue pointers indicate current location for each queue
— Automated queue modes initiated by:
– External edge trigger and gated trigger
– Periodic/interval timer, within QADC module [Queue 1 and 2]
– Software command
— Single-scan or continuous-scan of queues
— Output data readable in three formats:
– Right-justified unsigned
– Left-justified signed
– Left-justified unsigned
— Unused analog channels can be used as digital I/O
— Low pin-count configuration implemented
• Four 32-bit DMA timers
— 15-ns resolution at 80 MHz (66 MHz for MCF5214 and MCF5216)
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input-capture capability with programmable trigger edge on input pin
— Output-compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or reference-compare
— DMA trigger capability on input capture or reference-compare
• Two 4-channel general purpose timers
— Four 16-bit input capture/output compare channels per timer
— 16-bit architecture
— Programmable prescaler
— Pulse widths variable from microseconds to seconds
— Single 16-bit pulse accumulator
— Ability to boot from internal Flash memory or external memories that are 8, 16, or 32 bits wide (Continue..)

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