Product Descriptions

The 82551ER is an evolutionary addition to Intel’s family of 8255x controllers. It provides  excellent performance by offloading TCP, UDP and IP checksums and supports TCP segmentation  off-load for operations such as Large Send.

Its optimized 32-bit interface and efficient scatter-gather bus mastering capabilities enable the  82551ER to perform high speed data transfers over the PCI bus. This capability accelerates the  processing of high level commands and operations, which lowers CPU utilization. Its architecture  enables data to flow efficiently from the bus interface unit to the 3 KB Transmit and Receive  FIFOs, providing the perfect balance between the wire and system bus. In addition, multiple  priority queues are provided to prevent data underruns and overruns.

The 82551ER includes both a MAC and PHY. In also has a simple interface to the analog front end,  which allows cost effective designs requiring minimal board real estate. The 82551ER is pin  compatible with the 82559 family of controllers and is offered with software that provides  backwards compatibility with previous 82559ER controllers.

Product Features

 Enhanced IP Protocol Support 

— TCP, UDP, IPv4 checksum offload 

— Received checksum verification 

 Quality of Service (QoS) 

— Multiple priority transmit queues 

 Optimum Integration for Lowest Cost Solution 

— Integrated IEEE 802.3 10BASE-T and  100BASE-TX compatible PHY

— 32-bit PCI master interface 

— Thin BGA 15mm2 package 

 Integrated power management functions 

— ACPI and PCI power management standards  compliance 

— Wake on “interesting” packets and link status  change support 

 PHY detects polarity, MDI-X, and cable lengths.  Auto MDI, MDI-X crossover at all speeds 

 XOR tree mode support 

 High Performance Networking Functions 

— Early release 

— 8255x controller family chained memory  structure 

— Improved dynamic transmit chaining with  multiple priorities transmit queues 

— Full pin compatibility with the 82559 and  82559ER controllers 

— Backward compatible software to 82559ER  controllers 

— Full duplex support at 10 and 100 Mbps 

— IEEE 802.3u auto-negotiation support 

— 3 KB transmit and receive FIFOs

— Fast back-to-back transmission support with  minimum interframe spacing 

— IEEE 802.3x 100BASE-TX flow control  support 

— Adaptive Technology 

 Low Power Features

— Advanced Power Management (APM)  capabilities 

— Low power 3.3 V device 

— Efficient dynamic standby mode 

— Deep power-down support 

— Clockrun protocol support 

 82551ER Enhancements 

— Improved bit error rate performance 

— HWI support 

— Deep power-down state power reduction 

 Lead-free1 196-pin Ball Grid Array (BGA).  Devices that are lead-free are marked with a  circled “e1” and have the product code:  LUxxxxxx.

Actual product photos

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

We also provide ：