Product Descriptions

■ 32-Bit Parallel Architecture

— Two Instructions/clock Execution 

— Load/Store Architecture 

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers 

— Manipulates 64-Bit Bit Fields

— 11 Addressing Modes 

— Full Parallel Fault Model

— Supervisor Protection Model 

■ Fast Procedure Call/Return Model 

— Full Procedure Call in 4 Clocks 

■ On-Chip Register Cache 

— Caches Registers on Call/Ret 

— Minimum of 6 Frames Provided 

— Up to 15 Programmable Frames 

■ On-Chip Instruction Cache 

— 4 Kbyte Two-Way Set Associative 

— 128-Bit Path to Instruction Sequencer

— Cache-Lock Modes

— Cache-Off Mode

■ High Bandwidth On-Chip Data RAM 

— 1 Kbyte On-Chip Data RAM 

— Sustains 128 bits per Clock Access 

■ Selectable Big or Little Endian Byte  Ordering 

■ Four On-Chip DMA Channels

— 71 Mbytes/s Fly-by Transfers 

— 40 Mbytes/s Two-Cycle Transfers 

— Data Chaining — Data Packing/Unpacking 

— Programmable Priority Method 

■ 32-Bit Demultiplexed Burst Bus

— 128-Bit Internal Data Paths to and from Registers 

— Burst Bus for DRAM Interfacing

— Address Pipelining Option

— Fully Programmable Wait States 

— Supports 8-, 16- or 32-Bit Bus Widths 

— Supports Unaligned Accesses 

— Supervisor Protection Pin

■ High-Speed Interrupt Controller 

— Up to 248 External Interrupts 

— 32 Fully Programmable Priorities 

— Multi-mode 8-Bit Interrupt Port 

— Four Internal DMA Interrupts

— Separate, Non-maskable Interrupt Pin

— Context Switch in 625 ns Typical 

■ On-Chip Data Cache 

— 1 Kbyte Direct-Mapped, Write Through 

— 128 bits per Clock Access on Cache Hit

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Product Data Manual：

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