Product Features
■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532 – EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532 ■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
■ Enhanced ISP features – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) – ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices) – Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
Specifications
Attribute | Attribute value |
ANSM-Part# | ANSM-EPM7256AEQC208-7 |
Category | Integrated Circuits (ICs) |
Embedded | |
CPLDs (Complex Programmable Logic Devices) | |
Manufacturer | Altera |
Series | MAX® 7000A |
Packaging | Tray |
Part Status | Obsolete |
DigiKey Programmable | Not Verified |
Programmable Type | In System Programmable |
Delay Time tpd(1) Max | 7.5 ns |
Voltage Supply - Internal | 3V ~ 3.6V |
Number of Logic Elements/Blocks | 16 |
Number of Macrocells | 256 |
Number of Gates | 5000 |
Number of I/O | 164 |
Operating Temperature | 0°C ~ 70°C (TA) |
Mounting Type | Surface Mount |
Package / Case | 208-BFQFP |
Supplier Device Package | 208-PQFP (28x28) |
Base Product Number | EPM7256 |
Actual product photos
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