Product Features

■ Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration 

– MultiCoreTM architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory 

– LUT logic used for register-intensive functions 

– Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM) 

– ESB implementation of product-term logic used for combinatorial-intensive functions 

■ High density – 30,000 to 1.5 million typical gates (see Tables 1 and 2) 

– Up to 51,840 logic elements (LEs) 

– Up to 442,368 RAM bits that can be used without reducing available logic 

– Up to 3,456 product-term-based macrocells

■ Flexible clock management circuitry with up to four phase-locked loops (PLLs) 

– Built-in low-skew clock tree 

– Up to eight global clock signals 

– ClockLock® feature reducing clock delay and skew 

– ClockBoost® feature providing clock multiplication and division 

– ClockShiftTM programmable clock phase and delay shifting 

■ Powerful I/O features 

– Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits 

– Support for high-speed external memories, including DDR SDRAM and ZBT SRAM (ZBT is a trademark of Integrated Device Technology, Inc.) 

– Bidirectional I/O performance (tCO + tSU) up to 250 MHz 

– LVDS performance up to 840 Mbits per channel 

– Direct connection from I/O pins to local interconnect providing fast tCO and tSU times for complex logic 

– MultiVolt I/O interface support to interface with 1.8-V, 2.5-V, 3.3-V, and 5.0-V devices (see Table 3) 

– Programmable clamp to VCCIO 

– Individual tri-state output enable control for each pin 

– Programmable output slew-rate control to reduce switching noise – Support for advanced I/O standards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stubseries terminated logic (SSTL-3 and SSTL-2), Gunning transceiver logic plus (GTL+), and high-speed terminated logic (HSTL Class I) 

– Pull-up on I/O pins before and during configuration

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