Product Features

• Monolithic four channel SONET/SDH Payload Extractor/Aligner for use in STS-3 (STM- 1/AU-3) or STS-3c (STM-1/AU-4) interface applications, operating at serial interface speeds of 155.52 Mbit/s. 

• Provides integrated clock recovery and clock synthesis for direct interfacing with optical modules. 

• On each channel, provides termination for SONET section and line, SDH Regenerator Section and Multiplexer Section transport overhead, and path overhead of three STS-1 (STM- 0/AU-3) paths or a single STS-3c (STM-1/AU-4) path. 

• On each channel, maps three STS-1 (STM-0/AU-3) payloads or a single STS-3c (STM- 1/AU-4) payload to the system timing reference, accommodating plesiochronous timing offsets between the references through pointer processing. 

• Provides Time Slot Interchange (TSI) function at the Telecom Add and Drop buses for grooming 12 STS-1 (STM-0/AU-3) paths. 

• On each channel, provides clear-channel mapping of three 49.536 Mbit/s or 48.384 Mbit/s arbitrary data streams into an STS-3 (STM-1/AU-3) frame. Provides clear-channel mapping of a single 149.76 Mbit/s arbitrary data stream into an STS-3c (STM-1/AU-4) frame. 

• Supports line loopback from the line side receive stream to the transmit stream and diagnostic loopback from a Telecom Add bus interface to a Telecom Drop bus interface. 

• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. 

• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. 

• Low power 3.3 V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3 V and 5 V compatible. 

• Industrial temperature range (-40 °C to +85 °C). 

• 520 pin Super BGA package. 

• Complies with Telcordia GR-253-CORE (1995) jitter tolerance, jitter transfer and intrinsic jitter criteria.

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