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| General description The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 512 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Features and benefits ■ ARM7TDMI-S processor, running at up to 72 MHz. ■ Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access. ■ 64 kB of SRAM on the ARM local bus for high performance CPU access. ■ 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM. ■ 16 kB SRAM for general purpose DMA use also accessible by the USB. ■ Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem. ■ EMC provides support for static devices such as flash and SRAM as well as off-chip memory mapped peripherals. ■ Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts. ■ General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP serial interfaces, the I2S-bus port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers. ■ Serial Interfaces: ◆ Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. ◆ USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller. ◆ Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. ◆ CAN controller with two channels. ◆ SPI controller. ◆ Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA controller. ◆ Three I2C-bus interfaces (one with open-drain and two with standard port pins). ◆ I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. (Continue ...) Applications ■ Industrial control ■ Medical systems ■ Protocol converter ■ Communications |
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