Product Description
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DESCRIPTION The HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of 1,048,576x16. HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized withthe rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. FEATURES • Voltage: VDD, VDDQ 3.3V supply voltage • All device pins are compatible with LVTTL interface • 54 Pin TSOPII (Lead or Lead Free Package) • All inputs and outputs referenced to positive edge of system clock • Data mask function by UDQM, LDQM • Internal four banks operation • Auto refresh and self refresh • 4096 Refresh cycles / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CASLatency; 2, 3 Clocks • Burst Read Single Write operation |
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