Product Features
■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture
■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
■ High–density PLDs ranging from 600 to 10,000 usable gates
■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages
■ Hot–socketing support
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ Industrial temperature range
Product Specification
| Attribute | Attribute value |
| ANSM-Part# | ANSM-EPM3128ATC100-10N |
| Category | Integrated Circuits (ICs) |
| Embedded | |
| CPLDs (Complex Programmable Logic Devices) | |
| Manufacturer | Altera |
| Series | MAX® 3000A |
| Packaging | Tray |
| Part Status | Obsolete |
| DigiKey Programmable | Not Verified |
| Programmable Type | In System Programmable |
| Delay Time tpd(1) Max | 10 ns |
| Voltage Supply - Internal | 3V ~ 3.6V |
| Number of Logic Elements/Blocks | 8 |
| Number of Macrocells | 128 |
| Number of Gates | 2500 |
| Number of I/O | 80 |
| Operating Temperature | 0°C ~ 70°C (TA) |
| Mounting Type | Surface Mount |
| Package / Case | 100-TQFP |
| Supplier Device Package | 100-TQFP (14x14) |
| Base Product Number | EPM3128 |
Product Photos
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