Product Descriptions

The CY2309 is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

The CY2309 has two banks of four outputs each, which can be controlled by the select inputs as shown in Select Input Decoding on page 5. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes.

The CY2305 and CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0 μA current draw for these parts.

Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.

Product Features

■ 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies

■ Zero input-output propagation delay

■ 60-ps typical cycle-to-cycle jitter (high drive)

■ Multiple low skew outputs

❐ 85 ps typical output-to-output skew

❐ One input drives five outputs (CY2305)

❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)

■ Compatible with Pentium-based systems

■ Test Mode to bypass phase-locked loop (PLL) (CY2309)

■ Packages:

❐ 8-pin, 150-mil SOIC package (CY2305)

❐ 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)

■ 3.3 V operation

■ Commercial and industrial temperature ranges

Product Specification

Product Photos

For more product information, please download the PDF