Product Descriptions

The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Product Features

y JEDEC standard 3.3V power supply

y LVTTL compatible with multiplexed address

y Four banks operation

y MRS cycle with address key programs

- CAS Latency (2 & 3)

- Burst Length (1, 2, 4, 8 & full page)

- Burst Type (Sequential & Interleave)

y All inputs are sampled at the positive going edge of the system clock

y DQM for masking

y Auto & self refresh

y 15.6 μ s refresh interval

Product Photos

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