Product Features

- VDD/VDDQ = 1.50±0.075V

 - 1.5V center-terminated push/pull I/O

- 8n-bit prefetch DDR architecture

 - Differential clock inputs (CK, CK#)

- 8 internal banks 

- Nominal and dynamic on-die termination (ODT)

 for data, strobe, and mask signals

- Differential data strobe per byte of data(DQS/DQS#).

- DM masks write date at the both rising and falling edge of 

 the data strobe

- Programmable CAS READ latency (CL)

- Posted CAS additive latency

- Programmable CAS WRITE latency (CWL) based on tCK

- Fixed burst length (BL) of 8 and burst chop (BC) of 4

 (via the mode register set [MRS])

- Selectable BC4 or BL8 on–the-fly (OTF)

- Self refresh mode

- Tc of 0℃ to +95℃

 ∙ 64ms, 8192 cycle refresh at 0℃ to +85℃

 ∙ 32ms, 8192 cycle refresh at 85℃ to +95℃

 - Self refresh temperature (SRT)

 - Automatic self refresh (ASR)

 - Write leveling

 - Multipurpose register

 - Output driver calibration 

• Configuration

 - 128 Meg X 16 (16 Meg X 16 X 8 Banks).

• Timing – Cycle time

 - 1.07ns @ CL = 13 (-9M)

 - 1.25ns @ CL = 11 (-8K)

- 1.50ns @ CL = 9 (-6H)

- 1.87ns @ CL = 7 (-5F)

• Operating Temperature Ranges

 - Commercial (0℃ to +95℃)

 - Industrial (-40℃ to +95℃)

  Specifications

Actual product photos

Product Data Book：

For more product information, please download the PDF

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