Product Features

• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus

• 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

• 17-×17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation

• Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator

• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

• Data Bus With a Bus Holder Feature

• Address Bus With a Bus Holder Feature

• Extended Addressing Mode for 8M×16-Bit Maximum Addressable External Program Space

• 192K×16-Bit Maximum Addressable Memory Space (64K Words Program, 64K Words Data, and 64K Words I/O)

• On-Chip ROM with Some Configurable to Program/Data Memory

• Dual-Access On-Chip RAM

• Single-Access On-Chip RAM

• Single-Instruction Repeat and Block-Repeat Operations for Program Code

• Block-Memory-Move Instructions for Better Program and Data Management

• Instructions With a 32-Bit Long Word Operand

• Instructions With Two- or Three-Operand Reads

• Arithmetic Instructions With Parallel Store and Parallel Load

• Conditional Store Instructions

• Fast Return From Interrupt

• On-Chip Peripherals

• −  Software-Programmable Wait-State Generator and Programmable Bank Switching

• −  On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source

• −  Time-Division Multiplexed (TDM) Serial Port

• −  Buffered Serial Port (BSP)

• −  8-Bit Parallel Host Port Interface (HPI)

• −  One 16-Bit Timer

• −  External-Input/Output (XIO) Off Control to Disable the External Data Bus,Address Bus and Control Signals

• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes

• CLKOUT Off Control to Disable CLKOUT

• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic

• 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) for 3.3-V Power Supply)

• 10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (2.5-V Core)

• 8.3-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS) for 3.3-V Power Supply (2.5-V Core)

• Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

Product Specifications

Actual product photos

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

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