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Samsung plans to launch a new generation of memory HBM4 in 2025
2023-10-13

Samsung Electronics has said that it plans to start providing HBM3E samples, is developing HBM4, and aims to supply in 2025. According to Korean media, Sangjun Hwang, vice president of Samsung Electronics and DRAM development director of the memory business department, said recently that he planned to start providing HBM3E samples, and was developing HBM4, with the goal of supplying by 2025.


He disclosed that Samsung Electronics is also preparing to apply the NCF (non-conductive bonding film) assembly technology and HCB (hybrid bonding) technology optimized for high-temperature thermal characteristics to this product.


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In addition, Samsung also plans to provide cutting-edge customized turnkey packaging services. The company established an AVP (Advanced Packaging) business team earlier this year to strengthen cutting-edge packaging technology and maximize collaboration between business departments.


Industry institutions predict that the demand for HBM will increase by 58% annually in 2023 and is expected to grow by about 30% in 2024. Compared with traditional DRAM, HBM has advantages such as high bandwidth, high capacity, low latency, and low power consumption, which can accelerate AI data processing speed and is more suitable for high-performance computing scenarios such as ChatGPT. Therefore, it is highly favored, and storage giants are actively promoting the iteration of HBM technology.


Although HBM4 technology will make significant breakthroughs, its launch time will not be very fast, so it is still too early to discuss its application and popularization. Industry insiders point out that the current HBM market is mainly dominated by HBM2e, and in the future, HBM3 and HBM3e will become mainstream.


It is reported that HBM chip is a high bandwidth memory chip widely used in high-performance computing, data centers, artificial intelligence and other fields. The HBM chip adopts a 3D stacking process, stacking multiple DRAM chips together to achieve higher memory bandwidth and capacity, while reducing chip area, power consumption, and cost.


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