Recently, TSMC held the "2024 TSMC North America Technology Forum" in the United States, revealing its latest process technology, advanced packaging technology, and three-dimensional integrated circuit (3D IC) technology, using this leading semiconductor technology to drive innovation in the next generation of artificial intelligence (AI).
It is understood that TSMC unveiled its A16 (1.6nm) technology for the first time at this North American technology forum, combining leading nanosheet transistors and innovative backside power rail solutions to significantly improve logic density and performance. It is expected to be mass-produced in 2026.
TSMC has also launched System Level Wafer (TSMC SoWTM) technology, an innovative solution that brings revolutionary wafer level performance advantages to meet the future AI requirements of ultra large scale data centers.
It is reported that A16 will combine TSMC's super rail architecture with nanosheet transistors and is expected to be mass-produced in 2026.
Super rail technology can move the power supply network to the back of the wafer, freeing up more space on the front of the wafer, thereby improving logic density and performance, making A16 suitable for high-performance computing (HPC) products with complex signal wiring and dense power supply networks.
TSMC stated that compared to the N2P process, the A16 increases speed by 8-10% at the same Vdd (operating voltage), reduces power consumption by 15-20% at the same speed, and increases chip density by up to 1.10 times to support data center products.
In addition to A16, TSMC has also announced the launch of N4C technology, which continues N4P technology and reduces grain costs by up to 8.5% with a low adoption threshold. It is expected to be mass-produced in 2025.
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