Research institutions point out that it is expected that TSMC's monthly CoWoS production capacity will reach 40000 pieces by 2024 and further double by the end of next year. However, with the launch of Nvidia B100 and B200 chips, the production capacity of TSMC's CoWoS continues to be in short supply due to an increase in silicon interlayer area and a decrease in the number of 12 inch wafers cut out.
Chip enlargement
Jibang Consulting estimates that Nvidia's B-series (including GB200, B100, B200) will consume more CoWoS packaging capacity.
It is reported that TSMC has increased its CoWoS production capacity demand for the entire year of 2024, with an expected monthly production capacity of nearly 40000 pieces by the end of the year, an increase of over 150% compared to the total production capacity in 2023. The total production capacity is expected to nearly double in 2025.
However, the B100 and B200 chips released by Nvidia will have a larger interposer area than before, which means that the number of chips cut from 12 inch wafers will decrease, leading to CoWoS's inability to meet GPU demand.
HBM
Industry insiders say that HBM is also a major challenge, and the number of EUV layers is gradually increasing. Taking SK Hynix, the company with the highest market share in HBM, as an example, in 1 α Application of single-layer EUV during production, shifting towards 1 this year β, And it is possible to increase EUV applications by 3-4 times.
In addition to the increase in technical difficulty, with each iteration of HBM, the number of DRAMs in HBM also increases synchronously. The number of DRAMs stacked in HBM2 is 4-8, HBM3/3E increases to 8-12, and the number of DRAMs stacked in HBM4 will increase to 16.
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